This application is based on Japanese Patent Application No. HEI 11-345437 filed on Dec. 3, 1999, the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a semiconductor memory realized basing upon a new operation principle. Dynamic random access memories (DRAMs) are known as typical semiconductor memories. One bit data is stored in one memory cell of DRAM which is constituted of one MISFET and one capacitor. DRAMs having ultra fine memory cells and a high capacity are under developments. Semiconductor memories capable of realizing a still larger capacity have been desired to date.
b) Description of the Related Art
A flash memory has drawn attention as semiconductor memories capable of realizing a larger capacity. The flash memory is suitable for realizing a larger capacity because one memory cell is constituted of only one MISFET.
Data is stored in a flash memory by injecting carriers into a floating gate electrode of a floating gate type FET. In order to retain carriers injected into the floating gate electrode, the thickness of an insulating film between the floating gate electrode and the channel region is set to more than 8 nm. Carriers are injected via this insulating film into the floating gate electrode by applying a high voltage across the channel region and floating gate electrode. As a high voltage is applied between them, carriers are injected into the floating gate electrode by the Fowler-Nordheim tunneling (FN tunneling) phenomenon.
A voltage of about 10 to 20 V is required in order to inject carriers into the floating gate electrode by the FN tunneling phenomenon. It is therefore difficult to lower the voltage and reduce a power consumption.
It is an object of the present invention to provide a semiconductor memory capable of realizing a large capacity and a low voltage.
According to one aspect of the present invention, there is provided a semiconductor memory comprising: a semiconductor substrate; a tunneling insulating film formed on a partial surface area of said semiconductor substrate, said tunneling insulating film having a thinness enough to transmit carriers therethrough by a tunneling phenomenon; a floating gate electrode formed on said tunneling insulating film; a gate insulating film covering a side wall of said floating gate electrode and a partial surface area of said semiconductor substrate on both sides of said floating gate electrode, said gate insulating film having a thickness not allowing carriers to transmit therethrough by the tunneling phenomenon; a first control gate electrode disposed on said gate insulating film over the side wall of said floating gate electrode and over a partial surface area of said semiconductor substrate on both sides of said floating gate electrode; and a pair of impurity doped regions formed in a surface layer of said semiconductor substrate on both sides of a gate structure including said floating gate electrode and said first control gate electrode.
As a voltage is applied between the control gate electrode and impurity doped regions, carriers in the channel region tunnel through the tunneling insulating film and are injected into the floating gate electrode. Injected carriers change the threshold voltage so that data can be read. Carriers injected into the floating gate electrode do not tunnel through the gate insulating film.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory, comprising the steps of: forming a tunneling insulating film on a surface of a semiconductor substrate, the tunneling film having a thinness enough to transmit carriers therethrough by a tunneling phenomenon; forming a first conductive film on the tunneling insulating film, the first conductive film being made of conductive material or semiconductor material; forming a dielectric film on the first conductive film, the dielectric film having a thickness not allowing carriers to transmit therethrough by the tunneling phenomenon; forming a second conductive film on the dielectric film, the second conductive film being made of conductive material or semiconductor material; patterning a lamination structure from an upper surface of the second conductive film to at least a lower surface of the first conductive film to leave a laminated mesa including the first conductive film, the dielectric film and the second conductive film; forming a gate insulating film covering upper and side surfaces of the laminated mesa and a partial surface of the semiconductor substrate on both sides of the laminated mesa, the gate insulating film having a thickness not allowing carriers to transmit therethrough by the tunneling phenomenon; forming a third conductive film covering a whole surface of the gate insulating film, the third conductive film being made of conductive material or semiconductor material; anisotropically etching the third conductive film to leave a side control gate electrode made of the third conductive film over a side wall of the laminated mesa; doping impurities in a surface layer of the semiconductor substrate on both sides of a gate structure including the laminated mesa and the side control gate electrode to form impurity doped regions; and electrically connecting the side control gate electrode to the second conductive film constituting the laminated mesa.
The first conductive film constituting the laminated mesa operates as the floating gate electrode. The side control gate can be formed in a self-alignment manner relative to the floating gate electrode.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory, comprising the steps of: forming an element separation insulating film on a surface of a semiconductor substrate to define an active region surrounded with the element separation insulating film; forming a tunneling insulating film on the active region, the tunneling insulating film having a thinness enough to transmit carriers therethrough by a tunneling phenomenon; forming a first conductive member on the tunneling insulating film, the first conductive film traversing the active region and made of conductive material or semiconductor material; forming a gate insulating film on upper and side surfaces of the first conductive member and on a partial area of the active region on both sides of the first conductive member, the gate insulating film having a thickness not allowing carriers to transmit therethrough by the tunneling phenomenon; covering a surface of the gate insulating film with a conductive film made of conductive material or semiconductor material; anisotropically etching the conductive film to leave a side control gate electrode made of the conductive film over a side wall of the first conductive member; and doping impurities in a surface layer of the active region on both sides of a gate structure including the first conductive member and the side control gate electrode.
The first conductive film functions as the floating gate electrode. The side control gate can be formed in a self-alignment manner relative to the floating gate electrode.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory, comprising the steps of: forming an element separation insulating film on a surface of a semiconductor substrate to define an active region surrounded with the element separation insulating film; forming a first film over the whole surface of the semiconductor substrate; forming an opening through the first film, the opening traversing the active region; forming a gate insulating film on a surface of the active region exposed on a bottom of the opening, the gate insulating film having a thickness not allowing carriers to transmit therethrough by tunneling phenomena; forming a second film on bottom and side surfaces of the opening and on an upper surface of the first film, the second film being made of conductive material or semiconductor material; anisotropically etching the second film to leave side control gate electrode of the second film on the side surfaces of the opening and to expose a surface of the active region in a central area of the bottom of the opening; forming a tunneling insulating firm on the exposed surface of the active region, the tunneling insulating film having a thinness enough to transmit carriers therethrough by the tunneling phenomenon, and forming a dielectric film on a side wall of the side control gate electrode, the dielectric film having a thickness not allowing carriers to transmit therethrough by the tunneling phenomenon; forming a third film burying the opening and covering an upper surface of the first film, the third film being made of conductive material or semiconductor material; etching back the third film to remove the third film on the first film and to leave a floating gate electrode of the third film in the opening; removing the first film; and doping impurities in a surface layer of the active region on both sides of a gate structure including the side control gate electrode and the floating gate electrode.
The floating gate electrode can be formed in a self-alignment manner relative to the side control gate electrode.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory, comprising the steps of: forming an element separation insulating film on a surface of a semiconductor substrate to define an active region surrounded with the element separation insulating film; forming a dummy gate electrode on the active region, the dummy gate electrode traversing the active region; doping impurities in a surface layer of the active region on both sides of the dummy electrode; forming a first film over the semiconductor substrate, the first film covering the dummy gate electrode; removing the first film on an upper surface of the dummy gate electrode to expose the upper surface of the dummy gate electrode; removing the dummy gate electrode to expose a surface of the active region; forming a gate insulating film on the exposed surface of the active region, the gate insulating film having a thickness not allowing carriers to transmit therethrough by a tunneling phenomenon; forming a second film on a surface of the first film and on the gate insulating film, the second film being made of conductive material or semiconductor material; anisotropically etching the second film to leave a side control gate electrode of the second film on a side wall of the first film and to expose a surface of the active region in an area surrounded by the side control gate electrode; forming a tunneling insulating film on the exposed surface of the active region, the tunneling insulating film having a thinness enough to transmit carriers therethrough by the tunneling phenomenon, and forming a dielectric film on a side wall of the side control gate electrode, the dielectric film having a thickness not allowing carriers to transmit therethrough by the tunneling phenomenon; forming a third film burying a space surrounded by the side control gate electrode and covering an upper surface of the first film, the third film being made of conductive material or semiconductor material; and etching back the third film to remove the third film on the first film and to leave a floating gate electrode of the third film in the space surrounded by the side control gate electrode.
The floating gate electrode can be formed in a self-alignment manner relative to the side control gate electrode. Since impurities are doped before the gate electrode is formed, the gate electrode and dielectric film are not exposed to a high temperature process for impurity activation.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory, comprising the steps of: forming an element separation insulating film on a surface of a semiconductor substrate to define an active region surrounded with the element separation insulating film; forming a tunneling insulating film on the active region of the semiconductor substrate, the tunneling insulating film having a thinness enough to transmit carriers therethrough by a tunneling phenomenon; forming a first conductive member on the tunneling insulating film, the first conductive film traversing the active region and made of conductive material or semiconductor material; forming a side wall member on a side wall of the first conductive member; doping impurities in a surface layer of the active region on both sides of a mesa including the first conductive member and the side wall member; removing the side wall member; forming a gate insulating film on upper and side surfaces of the first conductive member and on a partial area of the active region on both sides of the first conductive member, the gate insulating film having a thickness not allowing carriers to transmit therethrough by the tunneling phenomenon; covering a surface of the gate insulating film with a conductive film made of conductive material or semiconductor material; and anisotropically etching the conductive film to leave a side control gate electrode made of the first conductive film over a side wall of the first conductive member.
The first conductive member functions as the floating gate electrode. The side control gate electrode is formed in a self-alignment manner relative to the floating gate electrode. Since impurities are doped before the side control gate electrode and gate insulating film are formed, the side control gate electrode and gate insulating film are not exposed to a high temperature process for impurity activation.
As above, since carriers can be injected into the floating gate electrode by direct tunneling, data read/write can be performed at a relatively low voltage. One memory cell is constituted of only one floating gate type FET. High integration is therefore possible. One of the floating gate electrode and control gate electrode can be formed in a self-alignment manner relative to the other. It is therefore possible to prevent a lowered yield to be caused by position misalignment.